The present invention relates to an operation of a nonvolatile memory device and, more particularly, to a method of erasing a nonvolatile memory device, which can perform an erase verify operation on an even bit line and an odd bit line at the same time.
A flash memory device, a type of nonvolatile memory device, generally includes a plurality of strings in each of which a plurality of memory cells is connected in series. The flash memory device has been widely used in a variety of semiconductor devices, such as portable electronic devices, including notebook computers, personal digital assistants (PDAs) and mobile phones, computer bios, printers, and universal serial bus (USB) memory.
A memory cell array of a typical flash memory device has a structure in which memory cells are connected in series between bit lines BL and a cell source line CSL. In a NAND flash memory device, two transistors, including a drain select line DSL and a source select line SSL, are connected to electrically connect a memory cell to the bit line BL and the cell source line CSL.
In a memory cell of the above NAND flash memory device, a data program operation and an erase operation are performed by Fowler-Nordheim (F-N) tunneling generated through a tunnel oxide layer between floating gates according to voltage applied to a control gate or a substrate (or a bulk, PWELL).
A nonvolatile memory device includes several memory blocks, each comprised of a plurality of memory cells, and performs an erase operation on a per memory-block basis. After the memory block is erased, the memory block is subject to a hard erase verify operation and then soft program and verify operations, so that the memory cells have a threshold voltage of almost 0V, which is lower than 0V.
In more detail, after an erase operation is performed by applying a high voltage to a substrate of the memory block, an even bit line is selected and an erase verify operation is performed on the memory block, and an odd bit line is selected and an erase verify operation is performed on the memory block. The erase verify operations performed on the even bit line and the odd bit line differ only in the selection of the bit line, but are performed in the same manner.
The erase verify operation is similar to a program verify operation except that the threshold voltage of memory cells is determined to be 0V or less. The erase verify operation is performed by precharging a bit line, performing evaluation, latching data according to a bit line voltage, and discharging the bit line voltage in this order. Erase verify pass or fail is determined based on the latched data.
If an erase verify operation is carried out in this manner, verification must be performed on even and odd bit lines separately. Accordingly, in view of a total erase operation, an actual erase time is short, but a verify time is relatively longer. This becomes a more significant problem in nonvolatile memory devices including multi-level cells. That is, the erase verify operation requires not only a process of performing soft program and soft program verify operations but also a hard erase verification. Accordingly, if the soft program operation is not performed well, the time taken to perform the soft program verify operation is lengthened.